1) Field of the Invention
This invention relates generally to fabrication of integrated circuit devices and more particularly to the fabrication of a memory device having embedded logic and more particularly to a memory device with embedded logic where the memory and logic FETs have different thickness gate oxide layers.
2) Description of the Prior Art
With the advent of Large Scale Integration (LSI) many of the integrated circuits formed on semiconductor substrates are comprised of several circuit functions on a single chip. For example, dynamic random access memory (DRAM), nonvolatile memory (NVM), and similar memory devices are composed of an array of memory cells for storing digital information, while the peripheral circuits on these devices are typically composed of logic circuits for addressing the memory cells. While other peripheral circuits function as read/write buffers and sense amplifiers.
To improve performance and optimize these devices, it is very desirable in the electronics industry to provide FETs that have both thin and thick gate oxides (dielectrics).
Typically, a thin gate oxide (dielectric) is used in the peripheral (logic) circuits to enhance FET device performance, while it is desirable to provide a thicker gate oxide for the higher gate voltage (Vg) requirements on the FET access transistors in the DRAM cells. More generally, there is a need to form devices with transistors having two different gate oxide (Dual gate oxide) thicknesses.
Typically, by the prior art, the dual-gate oxide is formed by thermally growing in the memory cell device area and in the logic device area (peripheral area), a first gate oxide on the substrate. A photoresist mask is then used to mask the gate oxide over the memory cell device area and the gate oxide is etched in the logic device area. The photoresist is then stripped and a second-gate oxide is grown on the logic device area, while the original gate oxide in the memory cell device area increases in thickness. Unfortunately, the inventor has found, by the method of the prior art, the presence of the photoresist over the gate oxide in the memory device area contaminates the oxide and degrades the device electrical characteristics. For example, one such contaminant is the mobile sodium (Na) ion in the gate oxide that can and does affect the long-term stability of the gate voltage (Vg) on the FET.
Therefore, there is still a strong need in the semiconductor industry for providing a thin gate oxide for the logic areas, and a thicker gate oxide for the memory areas without having the photoresist layer come into direct contact with the gate oxide, and by a method that does not substantially increase the manufacturing process complexity or cost.
An embedded Semiconductor Memory can increase bus width without increasing the pin counts of the package. Large bus width gives the embedded Memory an advantage in obtaining higher bandwidth. In the inventor's embedded memory, it is necessary to fabricate different thickness of gate oxide for 5.5V I/O and 3.3V/2.5V internal circuit to reduce power dissipation. There exist one major drawback in current technology for integrate dual gate oxide: Photoresist directly cover on the gate oxide and thus the oxide will be damaged more or less during removing photoresist process.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,672,521 (Barsan) that shows a method of forming multiple gate oxide thicknesses on a wafer substrate that uses doped and nitrogen I/I areas to enhance/retard oxide growth.
U.S. Pat. No. 5,658,812(Araki) aims to prevent the thickness of the element separation insulating film of the high voltage withstanding area from being thinned and reliability of the memory cell from being reduced. The patent forms photoresist layers over gate oxide regions to protect the regions from etches.
U.S. Pat. No. 5,532,181 (Takebuchi) shows a method of manufacturing semiconductor non-volatile memory device having different gate insulating thicknesses. A semiconductor non-volatile memory device includes a semiconductor substrate, insulating films formed on the semiconductor substrate and having at least two types of gate insulating films having different thicknesses.
U.S. Pat. No. 5,668,035 (Fang) shows a method for fabricating a dual-gate dielectric module for memory with embedded logic technology.
However, the prior art process can be further improved.